Lead Design Engineer

Analog Mixed-SignalLeadDesign Engineer(T3)- SerDes

Position Summary

We are seeking an Analog Mixed-SignalLeadDesign Engineer(T3)to develophigh-speed, low-powerSerDes transceivers for data-center, networking, AI, and high-performance computing applications. The engineer will translate system requirements intosilicon-readycircuit architecturesand collaboratewiththe architecture, digital, layout, verification, signal integrity, and post-silicon teams.

Key Responsibilities

• Design and verify high-speed SerDes blocks, including TX drivers, serializers, RX front ends, CTLEs, samplers, comparators, ADCs, DACs, PLLs, DLLs, clock dividers and distribution networks, regulators, bias circuits, and calibration loops.

• Translate link-level requirements into circuit specifications and optimize performance across PVT, mismatch, aging, and extractedparasitics.

• Develop behavioral models and support mixed-signal and top-level verification.

• Collaborate with layout and signal-integrity teams on physical implementation, channel/package effects, and post-layout signoff.

• Supporttapeout, silicon bring-up, characterization, debug, and production release.

• Document results and participate in technical design reviews.

Required Qualifications

• B.S. in Electrical Engineering or a related field with 3+ years of relevant experience, or an M.S. with 1+ years.

• Strong analog CMOS, noise, jitter, feedback, signal-integrity, and data-converter fundamentals.

• Hands-on transistor-level design experience with high-speed SerDes circuits.

• Excellent command of Cadence Virtuoso,Spectre,SpectreRF, ADE, parasitic extraction, and mixed-signal verification flows.

• Strong analytical, communication, collaboration, and engineering judgment.

Preferred Qualifications

• Experience with PAM4/NRZ SerDes, advanced CMOS orFinFETtechnologies, and standards such as Ethernet, PCIe, or CXL.

• MATLAB or C for architecture developmentSystemVerilogor Verilog-A for functional modeling and Perl or Python for automation.

• Experience using AI-assisted engineering tools responsibly for design exploration, verification, debugging, documentation, and workflow automation.

• Custom analog layout experience is a plus.

• Labcharacterizationexperience is a plus, along with experiencetaking mixed-signal IP from architecture throughtapeoutand silicon validation.

Success in This Role

The ideal candidate combinesstrong circuit intuition, disciplined verification,ownership, andclear communicationto deliverreliable, power-efficient SerDes solutions.