Lead CAD Integration & Validation Engineer – Analog/Mixed-Signal/RF

The

Lead CAD Integration & Validation Engineer – Analog/Mixed-Signal/RF operates in a Design Enablement role and is responsible for defining and executing comprehensive

pre-silicon verification strategies to support Analog/Mixed-Signal/RF SoC development. The role ensures seamless integration of foundry PDKs, process models, EDA views, CAD methodologies, and tools through

integration testing using AMS/RF IP cores as validation vehicles. The individual leads the development and execution of integration tests and CAD flow validation frameworks to evaluate compatibility, stability, scalability, and correctness across design platforms. This includes analysis, cross-version impact and performance assessment (PDK, tools, technology, methodologies), and end-to-end pre-silicon validation from schematic to sign-off to ensure consistency. The role collaborates with methodology teams, EDA tool vendors, and IP and design teams to drive new technology or feature enablement and deployment across 28nm to 5nm nodes, while leveraging automation and AI-driven techniques to improve robustness, productivity, and design quality.

Required Skillset

• Strong expertise in Analog, RF, and Mixed-Signal pre-silicon verification methodologies
• Good understanding of foundry PDKs, Process models, EDA views involved in simulation and validation process
• Good hands-on experience with Cadence Virtuoso, ADE, Spectre, AMS Designer, Keysight ADS and similar other industry standard tools
• Proficiency in RF and EM tools such as Keysight RFPro, Ansys HFSS, Cadence EMX, Clarity
• Experience with Analog and mixed signal modelling using spice, Verilog-A/MS, vams, wreal and co-simulation (Analog + Digital + RF domains)
• Experience in functional, structural, and integration-level verification
• Scripting skills in SKILL, TCL, Python, or similar
• Note: Out of Scope for this role: Post-silicon or hardware-level testing, development and validation using lab instruments, and standards compliance testing.

Desired Skillset

• Strong fundamentals in Analog and CMOS RF circuit blocks, such as amplifiers, PLLs, ADC/DACs, mixers, oscillators, filters, and RF front-end components
• Knowledge of reliability and aging analysis (BTI, HCI, EM effects)
• Understanding of Layout, parasitic effects, PVT variations, and post-layout verification

Soft Skills

• Strong technical leadership and mentoring capabilities
• Good problem-solving and analytical thinking
• Clear communication and documentation skills
• Ability to drive initiatives and influence technical decisions
• Strong ownership and accountability for deliverables

Academics & Experience Level

• Education: B.Tech/M.Tech in Electronics and Communication / Electrical and Electronics or related fields of engineering
• Experience: 8+ years of experience in Semiconductor / EDA domain More information about NXP in India...