Layout || Mask Designer

Job Description:

Role and Responsibilities:

• Develops and prepares stdcells layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering.
• Work may be completed through use of CAD or other computerized equipment.
• Checks dimensions, writes specifications, and verifies completed drawings, artwork or digitized plots.
• Check design layouts and detailed drawings.
• 3-5 years of experience.

Qualification/Requirements:

• Must have 3-5 of experience in standard cell layout, analog, mixed-signal and custom digital block designs in advanced CMOS process.
• Should have expertise in multiple standard cell layout library developments.
• Should be able to perform standard cell layout development and physical verification activities for complex designs as per provided specifications.
• Should have expertise in layout area and routing optimization, design rules, yield and reliability issues.
• Good understanding of layout fundamentals i.e., Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.
• Should have adequate knowledge of schematics, interface with circuit designer and CAD team. Understanding layout effects on the circuit such as speed, capacitance, power, and area etc., Excellent in problem-solving skills in solving area, power, performance, and physical verification of custom layout.
• Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Caliber- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.
• Should have leadership qualities and able to do multi-tasking as required.
• Should be able to work in a team environment and able to guide and provide technical support to the fellow team members.
• Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills. Knowledge of Skill coding and layout automation is a plus.
  

mandatory skillset:

stdcells layout || cadence virtuoso || physical verifications checks