BENGALURU · FULLTIME
Layout Engineer
Headway Tek Inc
Bengaluru · onsite · Posted 60d ago
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Not disclosed4–10 yrsfulltimeBengaluru
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Section · 01
About this role
Memory Layout Engineer
Experience: 4–10 years
Technology Nodes: TSMC/Samsung – 2nm, 3nm, 5nm, 7nm, and GF nodes
Qualifications: Bachelor's or Master's degree in Electrical Engineering.
Location - Bangalore
Key Skills & Responsibilities:
- Hands-on experience in layout of memory blocks like control logic, sense amplifiers, I/O blocks, bit cell array, decoders, etc.
- Strong experience in SRAM/DRAM, memory compiler IPs, and memory periphery circuits
- Expertise in top-level memory integration, DRC, LVS, density verification, and physical closure
- Understanding of IR/EM challenges in memory layouts
- Proficiency with Cadence/Synopsys tools for layout and Mentor/Cadence/Synopsys tools for physical verification
- Exposure to ultra-deep sub-micron design challenges and DFM guidelines
- Knowledge of memory architecture, bitcell layout concepts, and FinFET design rules
- Ability to optimize layout for area, power, speed, yield, and manufacturability
- Collaboration with circuit design, verification, PDK, and methodology teams
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Section · 02
Skills
Physical closurebitcell layout conceptsDRC LVS density verificationFinFET design rulesIR EM challenges in memory layoutslayout of memory blocksmemory periphery circuitsSRAM DRAM memory compiler IPstop-level memory integrationultra-deep sub-micron design challengesCadence Synopsys tools for layoutMentor Cadence Synopsys tools for physical verificationoptimize layout for area power speed yield and manufacturabilitycollaboration with circuit design verification PDK and methodology teamsMemory ArchitectureDFM guidelines