Junior Design Verification Engineer

Junior Design Verification Engineer (0-2 Years)

Position details

• Company: Raiton Semiconductor Pvt. Ltd.
• Location: Bangalore, India (client-site / hybrid, as per project)
• Experience: 02 years in ASIC/SoC functional verification (fresh graduates with strong project or internship experience are welcome)
• Employment type: Full-time
• Apply to: [email removed]

Role summary

• Own block- and subsystem-level verification for IPs and SoC subsystems built on industry-standard protocols.
• Develop and maintain UVM environments; write and debug tests; drive coverage closure.
• Work directly with design, architecture and client teams to sign off features on schedule.
• Write C-based tests for processor-driven verification where the program requires it.
• Contribute to functional-safety verification activities on automotive programs.

Key responsibilities

• Understand design specifications and protocol standards; contribute to verification plans, test lists and coverage models.
• Write UVM sequences, tests and checkers within existing testbenches; build new agents or scoreboards for smaller blocks.
• Develop C bare-metal tests for CPU-driven verification of RISC-V or ARM subsystems (boot, memory-map access, interrupts, DMA, peripheral programming).
• Verify blocks and interfaces in one or more of: RISC-V/ARM processor subsystems, DDR4/DDR5/LPDDR5 and HBM memory controllers, PCIe endpoints/root ports.
• Verify AMBA-based interconnects and peripherals (AXI, AHB, APB), including protocol checking and transaction-level scoreboarding.
• Debug simulation failures to root cause using waveform and log analysis; file and track issues with design teams.
• Add functional coverage and SystemVerilog Assertions; analyze coverage reports and write tests to close holes.
• Run regressions, triage failures and keep regression health reports up to date.
• Document tests, results and status clearly for internal and client reviews.

Required skills and experience

• 0–2 years of experience in ASIC/SoC/FPGA functional verification, or strong academic/internship projects in verification.
• Good knowledge of SystemVerilog and UVM: classes, constraints, randomization, sequences, drivers/monitors, scoreboards, factory and config DB.
• Working knowledge of C: pointers, structures, bit manipulation, memory-mapped register access; ability to write and debug bare-metal test code.
• Exposure to at least one of: RISC-V or ARM processor subsystems, DDR/LPDDR or HBM memory controllers, PCIe.
• Good understanding of AMBA bus protocols (AXI, AHB, APB): channels, handshakes, bursts, ordering and response handling.
• Strong digital design fundamentals: FSMs, FIFOs, arbitration, clock-domain crossing, reset, timing basics.
• Familiarity with functional coverage and SystemVerilog Assertions.
• Hands-on with at least one simulator (VCS, Xcelium or Questa) and a waveform debugger (Verdi or equivalent).
• Basic scripting in Python, Perl or Tcl; comfortable in a Linux environment.
• Familiarity with Git or Perforce.
• Clear communication, willingness to learn protocols in depth, and ability to work in a client-facing team.

Good to have

• Internship or project work on UVM testbench development for a real IP or subsystem.
• Exposure to RISC-V ISA (RV32/RV64, privileged spec) or ARM Cortex-A/M/R architecture.
• Exposure to DDR/LPDDR/HBM protocol basics: commands, timing parameters, refresh, training.
• Exposure to PCIe basics: TLP/DLLP, link training (LTSSM), configuration space.
• Awareness of low-power (UPF) or gate-level simulation concepts.
• Exposure to functional safety (ISO 26262) or fault simulation.
• Participation in RISC-V, VLSI or verification contests, open-source hardware projects, or relevant certifications.

Education

• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI or Computer Engineering , or equivalent.