JR for AMS Layout Engineer

About the Role

Cyient Semiconductor is seeking talented Analog Layout Engineers with strong experience in 28nm and higher technology nodes (40nm/55nm/65nm/90nm/180nm). The ideal candidate will have hands-on expertise in custom analog layout implementation, physical verification, and successful tape-out support for high-performance analog and mixed-signal IPs.

This role offers an excellent opportunity to work on complex analog circuits and advanced semiconductor products with leading global customers.

Key Responsibilities

• Develop high-quality custom analog and mixed-signal layouts from schematic to tape-out.
• Work on layout implementation for:
  • Amplifiers
  • Comparators
  • Bandgap References
  • LDOs
  • PLLs
  • ADC/DACs
  • PMIC Blocks
  • SerDes Analog Blocks
• Perform device matching, symmetry, shielding, and parasitic-aware layout techniques.
• Execute floorplanning and optimization to meet performance, area, and reliability requirements.
• Perform and resolve:
  • DRC
  • LVS
  • ERC
  • Antenna Checks
  • Density Checks
• Collaborate closely with Analog Design, Verification, Reliability, and Foundry teams.
• Support post-layout extraction (PEX) activities and layout-related debugging.
• Drive layout closure and support tape-out activities.
• Ensure compliance with process design rules and reliability requirements.

Required Technical Skills

Layout Expertise

• Strong hands-on experience in Analog Custom Layout.
• Expertise in matching-sensitive layouts.
• Common-centroid layout techniques.
• Interdigitation techniques.
• Guard Rings, Shielding, Isolation methodologies.
• ESD and Latch-up aware layout practices.

Technology Node Experience

Mandatory experience in one or more of the following nodes:

• 28nm
• 40nm
• 55nm
• 65nm
• 90nm
• 180nm

EDA Tools

• Cadence Virtuoso Layout XL
• Virtuoso ADE (Preferred)
• Calibre DRC/LVS/ERC
• Assura/PVS (Preferred)

Preferred Qualifications

• Experience in PMIC, Automotive, Consumer, Industrial, or High-Speed Analog products.
• Exposure to analog mixed-signal SoC environments.
• Experience supporting multiple tape-outs.
• Strong understanding of layout-dependent effects (LDE), electromigration (EM), and reliability considerations.
• Knowledge of FinFET technologies will be an added advantage.

Educational Qualification

B.E / B.Tech / M.E / M.Tech in Electronics, ECE, Electrical Engineering, VLSI, Microelectronics, or related disciplines.