Hi,

Greetings from Intellexe Management Consultants

Thank you for being associated with us.

We have an urgent opening with one of our esteemed clients for the following position

Job Description – DFT Engineer

Location: Bangalore

Total Experience: 3–15 Years

Relevant Experience: Hands-on experience in DFT (Design for Testability)

Key Skills & Technical Requirements

Candidates should have a strong understanding of DFT concepts and hands-on experience in one or more of the following areas:

• DFT Fundamentals: BSCAN, MBIST, Scan, ATPG
• DFT Implementation: MBIST Insertion, Scan Insertion, ATPG Pattern Generation
• Simulation & Debug: ATPG Simulation, MBIST Simulation, BSCAN Simulation, Zero-Delay Simulation, SDF Timing Simulation
• DFT Tools: Siemens Tessent, Synopsys, Cadence
• Simulation Tools: VCS, NC-Sim, Xcelium
• Fault Models: Stuck-at Faults, Transition Delay Faults (TDF), IDDQ
• Test Coverage: Scan Test Coverage Improvement, Fault Coverage Analysis
• SoC-Level DFT: OCC/OPCG Insertion, EDT/Scan Compression Logic Insertion, Clock Module Handling for Scan
• Post-Silicon & Production: Silicon Bring-Up, Production Testing, Tester Debug, Shmoo Plots and Graph Analysis
• Timing Constraints: Test-Mode Timing Constraints, STA and Physical Design (PD) Coordination

Candidate Skill Matrix – Years of Experience Mandatory

Candidates are requested to fill in their hands-on experience against each skill. Please enter 0 if there is no experience and distinguish hands-on experience from basic knowledge or exposure.

S. No.

Technical Skill / Keyword

Years of Experience

1

Overall DFT Experience

2

BSCAN

3

MBIST

4

MBIST Insertion

5

MBIST Simulation

6

Scan Insertion

7

ATPG Pattern Generation

8

ATPG Simulation & Debug

9

Zero-Delay Simulation

10

SDF Timing Simulation

11

Siemens Tessent

12

Synopsys DFT Tools

13

Cadence DFT Tools

14

VCS Simulator

15

NC-Sim Simulator

16

Xcelium Simulator

17

Stuck-at Fault Model

18

Transition Delay Fault (TDF)

19

IDDQ Testing

20

Scan Test Coverage Improvement

21

SoC-Level DFT

22

OCC/OPCG Insertion

23

EDT/Scan Compression Logic Insertion

24

Clock Module Handling for Scan

25

Post-Silicon Bring-Up

26

Production Test Activities

27

Tester Debug

28

Shmoo Plot / Graph Analysis

29

Test-Mode Timing Constraints

30

STA/PD Team Coordination

Additional Candidate Details

• Total Experience:
• Relevant DFT Experience:
• Current Company:
• Current CTC:
• Expected CTC:
• Notice Period / Earliest Joining:
• Current Location:
• Date of Birth:
• Contact Number:
• Alternate Email ID:

Application Process

Interested candidates matching the requirements are requested to share their updated resume and completed skill matrix, along with the above details.

Email:[HIDDEN TEXT]

If your profile matches the above requirements, please share your updated resume along with the

completed skill matrix and the following details:

Candidate Details

Total Experience:

Relevant Experience:

Current CTC:

Expected CTC:

Notice Period / Earliest Joining:

Date of Birth (Mandatory):

Current Company:

Current Location:

Alternate Email ID:

Contact Number:

Please email your profile to [HIDDEN TEXT].

We look forward to hearing from you.

Have a great day!

Best Regards,

Jaipal

Intellexe Management Consultants

[HIDDEN TEXT]