IP RTL Design Leader

We are seeking an experienced and motivated System IP RTL Design Lead to drive the definition and implementation of complex datacenter class IP for our next-generation semiconductor products. The ideal candidate possesses a deep understanding of System IP and SoC architecture, IP integration challenges, and is adept at leading a design team to deliver high-quality, scalable IP solutions. This role requires strong hands-on technical leadership, excellent communication skills, and a proven track record in the successful delivery of silicon IP.

This role ishybrid, based out of Bangalore, India.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A seasoned IP / SoC design leader with 15+ yrs of strong expertise in complex SoC architectures, high-speed protocols, and large-scale IP integration.
• Skilled in RTL design and debug (Verilog/SystemVerilog) with hands-on experience using industry-standard tools for simulation, synthesis, lint, CDC, and power analysis on high-frequency designs.
• Experienced in driving microarchitecture decisions, authoring design specifications, and performing complex PPA trade-off optimizations.
• A proactive problem solver capable of debugging complex logic across hierarchical levels within pre-silicon simulation, emulation, and post-silicon bring-up environments.
• A collaborative technical leader who can work seamlessly across architecture, design, verification, physical design, software, firmware and external IP vendors.
• Strong communication skills and the ability to mentor and guide engineering teams.

What We Need

• Lead the technical definition, selection, and integration of internally and third party developed IPs including MMUs, Interrupt controllers, Interconnects, Memory controllers, and peripherals within advanced SoCs.
• Define system-level requirements, IP specifications, interfaces, and integration methodologies to achieve performance, power, and area (PPA) goals.
• Drive IP design through sign-off activities while ensuring compliance with functional, security, and quality requirements.
• Bring deep expertise in protocols and interfaces such as AXI/AHB/APB, PCIe, DDR, and USB, along with scripting and verification methodologies including Python, Tcl, UVM, and formal verification.

What You Will Learn

• Work on cutting-edge CPU and AI compute architectures integrating advanced compute, memory, and interconnect technologies.
• Gain exposure to large-scale system integration challenges spanning RTL, verification, physical design, and silicon bring-up.
• Influence key architectural and microarchitectural decisions that directly impact next-generation product performance and scalability.
• Collaborate with highly experienced global engineering teams across multiple domains and disciplines.
• Contribute to the evolution of scalable IP integration methodologies, verification flows, and best practices for future SoC programs.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.