IP RTL Design Engineers

About Samsung Semiconductor India Research (SSIR)

With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.

As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.

Build the digital technology behind the future of imaging.

Samsung ISOCELL image sensors are redefining mobile photography and enabling new possibilities in mobility and intelligent vision. At SSIR, our CMOS Image Sensor team develops the advanced IPs and SoCs that power these innovations.

What you'll do

Design and develop complex, high-performance digital IPs and RTL for CMOS image sensors.

Translate specifications and architecture into robust, reusable RTL using Verilog/SystemVerilog/VHDL.

Drive module-level verification, simulation and formal verification.

Ensure design quality through Lint, CDC, DFT and other QC methodologies.

Perform synthesis, timing analysis and develop SDC constraints.

Apply low-power design techniques and contribute to power optimization.

Collaborate with architecture, verification, physical design, firmware and system teams to deliver IPs from spec to tape-out.

Contribute to improving design quality, performance, power, reusability and development methodologies.

Key skills

6+ years of digital logic / IP design experience.

Strong experience in complex RTL design using Verilog/SystemVerilog/VHDL.

Experience with Xcelium/VCS, Verdi and SpyGlass.

Knowledge of synthesis, timing constraints, timing analysis and low-power design.

Understanding of image processing, peripherals, buses/interconnects and power management.

Experience creating functional specifications and design documentation.

Experience with Magillem, Stratus/Catapult or HLS is an advantage.

Strong problem-solving skills and a collaborative, can-do attitude.

Education: B.E./B.Tech./M.E./M.Tech. in Electronics / Electrical Engineering

Location: Bangalore, India

Confidentiality Notice: Candidates are reminded that all proprietary information, trade secrets or confidential materials belonging to or obtained from their past or current employers must not be shared or used in connection with their application, interviews, or future employment with our organization