IP Physical Design Lead Engineer
NEWSOFT CONSULTANTS · Bengaluru · onsite · Posted 39d ago
₹35.0L - ₹80.0L PA8–10 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
Lead Analog IP PD tasks, such as floorplan, Bumpout, Power, IP integration
Execution of digital partitions: Synthesis to GDS, signoff (timing, physical verification, EMIR, Formal Equivalence, Low Power Verification)
Collaborate between PD, RTL team
Used Primetime, StarRC, Design Compiler, ICC
Constraints generation, STA, timing optimization/timing closure.
Exp of implementing design: synthesis to GDS
Execution of digital partitions: Synthesis to GDS, signoff (timing, physical verification, EMIR, Formal Equivalence, Low Power Verification)
Collaborate between PD, RTL team
Required Candidate profile
Exp on mixed signal IPs,such as PCIe/UCIE/DDRUsed Primetime, StarRC, Design Compiler, ICC
Constraints generation, STA, timing optimization/timing closure.
Exp of implementing design: synthesis to GDS
Sourced from naukri
Skills
Bumpoutfloor planningsynthesisIP Integrationpower deliverylow power verificationTimingformal