BENGALURU · FULLTIME
IP Logic Design Engineer
NEWSOFT CONSULTANTS
Bengaluru · onsite · Posted 39d ago
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₹40.0L - ₹80.0L PA8–10 yrsfulltimeBengaluru
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Section · 01
About this role
Implement RTL Design from (A-specs) architectural specs.
Execute IP RTL integration, IP level quality sign-off.
Quality checks such as functionality, lint/CDC,synthesis checks.
Define RTL methodology, coding standard, simulation flows, debug process
Solid SystemVerilog, RTL coding, Clock domain crossing, microarch/simulation debug, STA.
LINT, CDC/RDC, synthesis, timing, regression, code coverage. AMBA PCIe UCIe & DDR
Execute IP RTL integration, IP level quality sign-off.
Quality checks such as functionality, lint/CDC,synthesis checks.
Define RTL methodology, coding standard, simulation flows, debug process
Required Candidate profile
Deep PCIe/DDR/UCIE IP arch.Solid SystemVerilog, RTL coding, Clock domain crossing, microarch/simulation debug, STA.
LINT, CDC/RDC, synthesis, timing, regression, code coverage. AMBA PCIe UCIe & DDR
Sourced from naukri
Section · 02
Skills
CdcStatic Timing AnalysisDdrVerilogFPGAASICPCIEVHDLASIC DesignRTL CodingRTL Design