IP Design Verification Lead
NEWSOFT CONSULTANTS · Bengaluru · onsite · Posted 40d ago
₹35.0L - ₹80.0L PA8–10 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
Define analog IP verification strategy & test plan through specs (A-Spec) doc.
Develop testbench, components for Analog IP Data, Clock, Control Paths.
Lead 4-5 members
Defining/meeting a coverage goals
Adhering to coding guideline practices
DV life cycle, QOV, coverage goals
C++/SystemVerilog testbench
Exp in clocking reset/power-up sequence, power mgmt verification
Low power DV techniques
Develop testbench, components for Analog IP Data, Clock, Control Paths.
Lead 4-5 members
Defining/meeting a coverage goals
Adhering to coding guideline practices
Required Candidate profile
Analog IP/architecture, protocol PCIE DDR UCIEDV life cycle, QOV, coverage goals
C++/SystemVerilog testbench
Exp in clocking reset/power-up sequence, power mgmt verification
Low power DV techniques
Sourced from naukri
Skills
DdrSystem VerilogPCIETest BenchLow-Power DesignC plus plusUCIeclockingCoverage closure