Infra Formal Verification Sr Lead Engineer
Qualcomm · Bengaluru · onsite · Posted 29d ago
Undisclosed4–9 yrsfulltimeSourced from
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About this role
Company: Qualcomm India Private Limited
Job Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.
Job Area Engineering Group, Engineering Group > ASICS Engineering
Role Overview Qualcomm Infra and Periph team in India is part of a worldwide team responsible for developing and delivering Infra and Periph solutions which are setting the benchmark in Mobile/Compute/Automotive industry. The role of Infra and Periph Formal verification Engineer will involve Verification of the Infra and Peripheral RTL using industry standard Formal Verification tools and technologies based on latest model/equivalence checking algorithms. The role also requires close collaboration with worldwide design, systems and EDA/CAD teams. Hence, we are looking for candidates with strong communication skill both written and verbal. For better understanding of some of our products, please refer to the links below
Minimum Qualifications - Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
- Master's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- PhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
- Minimum 4-12 years of VLSI industry experience.
- Strong analytical skills to solve complex problems.
- Specialization in formal verification with tools like Jasper Gold or VC-Formal.
- Knowledge of cutting-edge formal verification methodologies and techniques.
- Able to implement abstraction techniques for effective verification.
- Hands-on experience with Verilog / System Verilog HDLs, temporal logic assertions, and able to understand complex RTL quickly.
- Proficient with scripting languages such as Perl, TCL and(or) Python.
- Bachelors - Computer Science
- Bachelors - Electronics and Communications Engineering
- Bachelors - Information Systems
- System Verilog Assertions
- Formal Verification
- System Verilog
- Verilog
- Temporal Logic Assertions
- Jasper Gold
- VC-Formal
- Perl
- Python
Sourced from naukri
Skills
ScriptingSOCformal verificationanalytical thinkingVLSIscripting languagesAnalogAutomotivePerlVerilogSystem VerilogASICASIC DesignCADautomotive industryEvent DrivenPythonAlgorithmsRest AssuredData Processing
About Qualcomm
Qualcomm
Semiconductors
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