Infra Design Verification Sr Engineer

Bachelor''s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORMaster''s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

• Develop and maintain UVM-based verification environments for high-speed interconnect protocols (PCIe, CXL, AXI).
• Create and execute verification plans for high-speed interconnect protocols including PCIe, CXL, AXI, and CHI.
• Perform block-level and top-level verification, including functional coverage, assertion-based verification, and regression testing.
• Collaborate with RTL designers, architects, and validation teams to ensure design correctness and coverage closure.
• Work closely with design and architecture teams to understand specifications and derive verification strategies.
• Use third-party VIPs (e.g., Synopsys, Mentor) for protocol compliance and simulation.
• Implement and enhance scoreboards, agents, monitors, and sequences.
• Integrate and validate SMMU and Coresight components in Subsystem environments.
• Drive verification closure through coverage convergence and assertion-based verification.
• Contribute to performance, power, and cost optimization considerations during verification.
• Mentor junior engineers and contribute to verification methodology improvements.
• Debug failures at RTL and gate-level simulations.

• Strong proficiency in System Verilog, UVM, and verification methodologies.
• Deep understanding of PCIe Gen3/Gen4/Gen5/Gen6, CXL 1.1/2.0/3.0, AXI/CHI protocols, and SMMU/Coresight architecture.
• Familiarity with Synopsys/Mentor VIPs for PCIe/CXL and AMBA protocols.
• Expertise in assertion-based verification (SVA) and coverage-driven testing.
• Proficiency in Perl/Python/Tcl scripting for automation.
• Knowledge of power-aware verification (UPF), formal verification, and performance/power optimization.
• Experience with coverage-driven verification and random constraint-based testing.
• Experience with scripting languages like Python, Perl, or Tcl.

• Bachelors/Masters/Ph.D. in Electrical, Electronics, or Computer Engineering.
• 3-6 years of ASIC/Subsystem/SoC verification experience.
• Experience with PCIe, USB, Ethernet, or other peripheral protocols is a plus.
• Exposure to post-silicon validation and lab bring-up is desirable.