Hiring Design Verification Engineers (C/C++) | Mirafra Technologies

Mirafra Technologies is Hiring Design Verification (C/C++) Engineers

Location: Hyderabad
Experience: 3 to 8 Years
Notice Period: 0 to 30 Days

Mirafra Technologies is looking for talented Design Verification Engineers with strong hardware verification expertise, software development skills, and exposure to AI/ML-driven verification methodologies.

Key Responsibilities

• Verify Control & Status Registers (CSR) and memory-mapped I/O blocks.
• Develop and execute verification plans using SystemVerilog, UVM, and RAL.
• Validate register functionality, reset values, access policies, and protocol compliance.
• Work on AXI/APB/AHB protocol verification.
• Develop test cases and automation using C/C++ and Python.
• Collaborate with RTL, firmware, and architecture teams.
• Contribute to AI/ML-based verification, regression optimization, and coverage closure.

Required Skills

3+ years of Hardware Verification experience
Strong knowledge of SystemVerilog, UVM, and RAL
Experience with AXI/APB/AHB protocols
Proficiency in Python and C/C++
Experience with VCS, Xcelium, or Questa
Strong debugging and SoC verification skills

Preferred Skills

AI/ML exposure or experience working with AI Agents
Firmware-Hardware Co-verification
Formal Verification methodologies
SystemRDL/IP-XACT knowledge

Must-Have Skills

• Hardware Verification
• Software Development (C/C++/Python)
• AI/ML Exposure

Interested candidates can share their updated resumes to: [email removed]