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    Job · 20755719

    HYDERABAD · FULLTIME

    Hardware-Software Integration & Verification Engineer

    AMD Telecom

    AMD Telecom

    Hyderabad · onsite · Posted 11d ago

    Sourced fromFoundit
    Not disclosed8–10 yrsfulltimeHyderabad

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    Section · 01

    About this role

    ADVANCE YOUR CAREER. ADVANCE THE WORLD.

    At AMD, we believe technology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

    Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we'll advance your career.

     

    The Role

    The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's graphics processor IP, resulting in no bugs in the final design.  

     

    THE PERSON: 

    You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

     

    KEY RESPONSIBILITIES: 

    • Collaborate closely with RTL designers, architects, verification engineers, and firmware teams to improve register development workflows.
    • Develop, enhance, and maintain register methodology and automation tools used across SoC/IP development teams.
    • Develop software solutions, scripts, and frameworks that automate register generation, validation, documentation, and verification flows
    • Debug and resolve issues related to register implementation, generation flows, and tooling infrastructure 
    • Mentor engineers on register methodologies, automation practices, and software engineering best practices

     

    PREFERRED EXPERIENCE: 

    • 8-10 years of experience in semiconductor design, with a strong background in RTL design and design methodologies.
    • Hands-on expertise in RTL design using Verilog/SystemVerilog.
    • Strong software development skills in Python; experience with C++, Java, or similar programming languages is a plus
    • Proficient in debugging firmware and RTL code using simulation tools 
    • Strong problem-solving skills with the ability to work across hardware and software domains.
    • Understanding of UVM methodology is good to have
    • Familiarity with IPXACT or SystemRDL is a plus.
    • Scripting language experience: Perl, Ruby, Makefile, shell preferred. 
    • Experience with version control systems (Git/Perforce), CI/CD pipelines, and modern software development practices  

    ACADEMIC CREDENTIALS: 

    • Bachelors or Masters degree in computer engineering/Electrical Engineering

    Benefits offered are described: AMD benefits at a glance.

    AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

    AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available here.

    This posting is for an existing vacancy.

    Sourced from foundit

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    Section · 02

    Skills

    PerlrubyVerilogSystem VerilogRTL DesignMakefileUVM methodologyPerforceIP-XACTPythonJavaGITSystem RDL

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