Graduate Engineer Trainee - Physical Design

Qualification:

• B.E./B.Tech/M.Tech in ECE, EEE, EIE, VLSI & Microelectronics or related fields
• VLSI Physical Design training preferred

Skills Required:

• ASIC Physical Design Flow
• Floorplanning, Placement, CTS, Routing
• STA, Timing Closure, DRC/LVS
• CMOS & Semiconductor Fundamentals

Preferred Tool Exposure:

• Cadence Innovus/Tempus
• Synopsys ICC2/PrimeTime
• Mentor Calibre

Role: Work on ASIC Backend Physical Design activities including Floorplanning, Placement, CTS, Routing, Timing Analysis, Physical Verification, and Design Optimization using industry-standard EDA tools.

Ideal Candidate: Freshers or candidates with up to 3 years of experience, strong PD fundamentals, and hands-on VLSI training/projects.