Functional Verification Engineer

Required Professional and Technical Expertise9 + years of experience in Functional Verification of processors or ASICs.

Minimum 9+ years of experience in any of the following Experience with 3rd party IP blocks: DDR, PCI, NAND, or AXI.

Self-Starter, ready to move quickly to keep the design moving forward.

IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc .AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification.

Gate level simulation and emulation. Track record in leading team.

Clock domain crossing and reset domain crossing verification .

Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ .Knowledge of HDLs (Verilog, VHDL) .

Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl.

Worked on multiple levels of verification (unit/element/sub-system/system level).

Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow.

Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails

As a Functional verification engineer, you will be working on IBM SOC or ASICs used in IBM servers. Leading the development of the verification environment, testbenches and writing testcases. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design. Work with development team to ensure coverage criteria is met.