Functional Verification Engineer

Project Role : Functional Verification Engineer

Project Role Description : Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.

Must have skills : SoC Verification

Good to have skills : NA
Minimum 3 year(s) of experience is required

Educational Qualification : 15 years full time education

Summary:
As a Functional Verification Engineer, a typical day involves designing and implementing comprehensive testbenches to validate the functional accuracy of digital designs at both block and system levels. The role includes crafting various types of tests such as constrained-random, directed, and coverage-driven to thoroughly assess design behavior. Collaboration with design and architecture teams is a key part of the day, focusing on identifying edge cases and ensuring exhaustive functional coverage prior to tape-out. This position requires a proactive approach to problem-solving and continuous communication within the team to maintain high-quality verification standards.

Roles Responsibilities:

Expected to perform independently and become an SME.

Required active participation/contribution in team discussions.

Contribute in providing solutions to work related problems.

Assist in documenting verification plans and results to support design reviews and audits.

Support junior team members by sharing knowledge and providing guidance on verification methodologies.

Engage in continuous learning to stay updated with the latest verification techniques and tools.

Collaborate effectively with cross-functional teams to ensure alignment on project goals and timelines.

Professional Technical Skills:

Must To Have Skills:

Proficiency in SoC Verification.

Strong understanding of verification methodologies including constrained-random and coverage-driven testing.

Experience with SystemVerilog and Universal Verification Methodology for testbench development.

Ability to analyze complex digital designs and identify potential corner cases.

Familiarity with simulation tools and debugging techniques to ensure design correctness.

Capability to work with design and architecture teams to enhance verification coverage and quality.

The candidate should have minimum 3 years of experience in SoC Verification.

This position is based at our BDC6F - SEZ office.

A 15 years full time education is required.

Qualification 15 years full time education