HYDERABAD · FULLTIME
FPGA Validation Engineer

ACL Digital
Hyderabad · onsite · Posted 15d ago
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Section · 01
About this role
FPGA Validation Engineer
Experience : 1-2 year Location : Hyderabad highly technical team that develops test plans, completes functional & electrical validation, & debugs issues for new processor silicon interface features with strong focus on power management. Writes comprehensive electrical & functional test plans for the processor interface validation of processors. Executes electrical & functional test plans for client processors using hardware & software validation tools, oscilloscopes, & logic analyzers. Debug of electrical & functional issues for new processors. Provides detailed input into the platform definition & review of platform designs used in the silicon validation of new processors. Provides technical guidance and training to less experienced engineers and technicians in the planning, test, & debug processor. RTL Verilog/VHDL, FPGA Design & debug Xilinx/Altera, board bring up & debug. Interested,please share your updated resume to janagaradha.n@acldigital.com
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Section · 02
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About ACL Digital

ACL Digital
IT Services & Consulting
1.8k+
employees
1992
34 years old
Santa Clara, California
United States (USA)
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