FPGA Design Engineer Vivado Implementation & STA

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.

Job Title: Engineering - Verification Engineer 1

Location: Hyderabad

Duration: 12 Months

Job Description:

To validate, test Vivado Implementation flow stages like placer, Static Timing Analysis. Person expected to have prior Vivado tool knowledge and FPGA flow awareness. Any EDA company experience is nice to have

Digital design, Logic Design, STA, Design Constraints, Debug skills are basic requirements

Qualifications & Experiences:

• Bachelors or Masters in ECE, EE, EI, VLSI
• Min 2yrs, Max 4yrs
• Experience in Xilinx Vivado flow, specifically Implementation tool flow
• Experience in FPGA design flow, STA, Logic and System design
• Good to have automation skills and AI usage knowledge