FPGA and RTL Design Engineer

Responsibilities

• Design, develop, and verify FPGA-based systems.
• Write and test RTL code using Verilog, SystemVerilog, or VHDL.
• Perform timing analysis, timing closure, and debugging.
• Implement DSP algorithms, filtering, and FFT on FPGAs.
• Debug FPGA boards and perform hardware validation.

Requirements

• FPGA design, development, or verification experience.
• Strong knowledge of digital design, FSMs, CDC, and timing analysis.
• Experience with FPGA boards from AMD/Xilinx, Microchip, or Intel/Altera.
• Familiarity with Vivado, Libero SoC, Quartus Prime, or ModelSim/QuestaSim.
• Hands-on experience with FPGA debugging tools and lab equipment.
• Knowledge of DSP, high-speed interfaces, and low-power design is an advantage.