PUNE · FULLTIME
Formal verification engineer
Sourceright Technologies
Pune · onsite · Posted 70d ago
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Undisclosed4–9 yrsfulltimePune
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Section · 01
About this role
Position: Formal verification engineer (IRT40ST RM 4299)
Job Description
- Experience with Formal Verification (e.g., sequential equivalence checking, Security Path verification, connectivity, low power and Formal property verification).
- Experience with programming languages (e.g., Python/Perl and TCL).
- Experience with at least one formal verification tool (e.g., Cadence Jasper, Synopsys VC-Formal).
- Expertise in property specification languages (e.g., SVA, PSL), as well as proficiency in HDLs such as System Verilog, Verilog or VHDL.
Job Category: Embedded HW_SW
Job Type: Full Time
Job Location: Bangalore Pune Hyderabad
Experience: 4+ years
Notice period: 0-30 days
Disclaimer: This job description has been sourced from a public domain and may have been modified by Naukri.com to improve clarity for our users. We encourage job seekers to verify all details directly with the employer via their official channels before applying.
Disclaimer: This job description has been sourced from a public domain and may have been modified by Naukri.com to improve clarity for our users. We encourage job seekers to verify all details directly with the employer via their official channels before applying.
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Section · 02
Skills
formal verificationCadenceprogramming languagesPerlProgrammingVerilogSystem VerilogsynopsysEmbedded SystemsPython