FE RTL lead

FE RTL lead

Location: Bangalore

• SoC RTL Design Engineer with 8 – 12 years experience
• Expertise in writing RTL in Verilog and System Verilog
• Knowledge of ARM based bus protocols like CHI, AXI, AHB, APB, PCIe is must
• Hands-on experience in integration of PCIe and Ethernet IPs, chip IO integration
• Hands-on experience in design static checks like Lint, CDC, RDC, CLP, UPF
• Working knowledge of GIT is preferred
• Education: Master's degree or equivalent in EE or Computer Engineering (CE)
• Excellent analytical, and problem-solving skills

Mandatory skills:

• Experience in ARM Architecture based SoC design
• Any candidate with PCIE/USB/Ethernet experience is good.
• Prior experience with Lint, CDC STA, UPF, CLP tools is must.

Note: Candidates with 8 – 12 years should have the following skills.

• Should have good understanding of SoC design flows
• Good technical leadership skills with ability to guide the team members on SoC execution
• Expertise in SoC architecture and mapping the architecture spec to implementation level details

Excellent communication skills is a must