BENGALURU · FULLTIME
Engineer II - CAD
Microchip Technology
Bengaluru · onsite · Posted 4d ago
Sourced from
Undisclosed2–8 yrsfulltimeBengaluru
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Section · 01
About this role
Job Summary
Responsibilities
Requirements
Qualifications
Travel Time
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
A successful candidate in this role will participate in various aspects of EDA support and developing next-generation ASIC design flow and methodology. He / She will also work closely with various business units across the globe to understand their needs and foster innovative ideas to solve complex problems.
Responsibilities
- A successful candidate in this role will participate in various aspects of EDA support and developing next-generation ASIC design flow and methodology.
- He / She will also work closely with various business units across the globe to understand their needs and foster innovative ideas to solve complex problems.
Requirements
- Good Knowledge of design flows from RTL design through synthesis, formal verification, and timing closure for RTL2GDS delivery.
- Design, benchmark, and deploy automated CAD tool flows focusing on logic synthesis, hierarchical optimization, physical synthesis, and chip sign-off timing.
- Automation Tools Customization: Write and optimize highly robust, scalable scripts using Tcl and Python to reduce Flow Turnaround Time (TAT) and build automated tracking tools for timing data.
- Synthesis Equivalence Verification: Build and optimize front-end flows utilizing advanced tools for logical/physical synthesis and Formal Verification/Logic Equivalence Checking (LEC).
- Hands-on experience with one or more of the following industry-standard toolsets: Synopsys Fusion Compiler, DC, PrimeTime, Cadence Genus, Tempus or Innovus.
- Exposure to leveraging AI driven EDA capabilities (e.g., Synopsys FC.ai, Cadence Cerebrus) to automate PPA exploration and timing closure optimization.
- Standardize and automate the validation of Synopsys Design Constraints (SDC) across all functional and test modes.
- Partner directly with major EDA vendors to test next-generation features, troubleshoot internal tool failures, and adapt flows for deep sub-micron advanced process nodes.
- Excellent verbal and written communication skills.
Qualifications
- B.E./B.Tech/M.E./M Tech (Electronics/ECE/CS/VLSI).
- 2 to 8 years of relevant experience is required
Travel Time
0% - 25%
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
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Section · 02
Skills
Automationformal verificationPrimetimeCadenceVLSItiming closureInnovussynthesiscompilerEmployee developmentASICASIC DesignRTL DesignCADcustomizationEvent DrivensynopsysPythonCommunication SkillsProduct DevelopmentArtificial Intelligence
Section · Company
About Microchip Technology
Microchip Technology
Semiconductors
2.1k+
employees
1989
37 years old
Chandler, Arizona
US
₹19.1L PA avg
Avg at Microchip Technology
About
Microchip Technology provides embedded control solutions, serving diverse sectors with tools that enhance design efficiency and reduce costs.
Industries
SemiconductorsInternet
Employee ratings
10 reviews
3.8/ 5
Culture
3.6
Career growth
2.8
Work-life
3.8
Employees rate it well for
Work-Life Balance43Company Culture38
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