CHENNAI · FULLTIME
Engineer ASIC Design / Verification
Callidus Systems
Chennai · onsite · Posted 58d ago
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Undisclosed3–8 yrsfulltimeChennai
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Section · 01
About this role
Looking for Engineers with more than 3+ years of experience in the field of VLSI Design, Architecture definition and Verification. Should have good coding skills is Verilog HDL, C/C++, Perl or Scripting language.
Exposure to Altera/Xilinx FPGA tools and PCI/PCIX standards will be an added advantage.
Exposure to Altera/Xilinx FPGA tools and PCI/PCIX standards will be an added advantage.
Educational Requirements: BE/BS or ME/MS.
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Section · 02
Skills
ScriptingXilinxVLSIVerilog HDLbsPerlVerilogASICASIC DesignVLSI DesignArchitectureFPGA tools