BENGALURU · FULLTIME
Emulation Engineer
Leadic Design
Bengaluru · onsite · Posted 30d ago
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Not disclosed7–9 yrsfulltimeBengaluru
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Section · 01
About this role
7+ years of experience in ASIC/SoC Emulation / Pre-Silicon Validation
Cadence Palladium(XP / Z1 / Z2 / Z3) Or ZeBu – Mandatory
Strong experience in Palladium or ZeBu compilation/build flows
Advanced Clocking, ICE & VIF flows
Strong programming skills in SystemC, C/C++
Scripting: Python, TCL, Perl & Shell
RTL: Verilog / SystemVerilog / VHDL
Debugging: Lauterbach, JTAG, Coresight/UltraSoC
SoC protocols: PCIe, DDR/LPDDR, AXI, USB, SPI
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Section · 02
Skills
Cadence Palladium XPspiDdrUSBtclcshellPerlVerilogSystem VerilogJTAGPCIEVHDLLpddrSystemcAxiReact Testing LibrarylauterbachZebuCadence PalladiumUltraSoCCoresightPython