EDA Staff SW Dev Eng (C++,PNR/Synthesis)

Job Summary


Accountabilities

• Develop and deliver state-of-art and software infrastructure for world-class ease-of-use FPGA software tool for small, mid-range and large FPGA products.
• Develop software capabilities for next generation of FPGA products.
• Support and maintain existing FPGA design tools.
• Contribute to Spec and Plan process - review marketing requirement documents, generate functional specifications and developer unit test plans to ensure quality software.
• Improve development methodologies and processes.
• Candidate will work on developing advanced security flows, like Isolation Design Flow and partial reconfiguration flows

Qualifications

• BS/MS/PhD Electrical Engineering or Computer Science
• 12+ years of experience in large-scale software development for engineering application domains preferably in FPGA/ASIC EDA domains.
• Must be proficient with C++. Modern C++ proficiency is a plus.
• Experience in partial reconfiguration flow is a plus
• Strong background in object-oriented programming, data structures and algorithms, and graph theory
• Experience of working on multiple platforms - at least Linux and Windows - is required.
• Knowledge of shell, TCL or Python scripting is a plus.
• Familiarity with commercial FPGA software tools and design flow is a plus. Knowledge in FPGA logic design is a plus.
• Must be detail oriented and possess independent problem-solving skills. Must be able to drive projects and lead a discussion.
• Strong written and verbal communication skills, and collaboration skill with the ability to work with multiple groups.

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