DV Lead Manager

Key Responsibilities

• Customer Stakeholder Engagement
• Leadership Team Management
• Experience in IP/SOC/Subsystem verificatio
• Coverage driven verification using UVM
• Strong System Verilog knowledge along with Assertion coding
• Strong debugging skills
• Excellent problem-solving and analytical skills
• Experience with verification methodologies and tools
• Knowledge of scripting languages such as Perl or Python
• Good communication and collaboration skills
• Working experience on protocol like , AXI / PCIe / CXL / Ethernet / DMAC / USB / UFS / MIPI

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.