DV Engineer
Aionsi · Bengaluru · onsite · Posted 58d ago
Undisclosed1–4 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
;Develop and debug UVM-based verification environments and drive regression and coverage closure.
;CORE RESPONSIBILITIES
- ;Develop and maintain UVM testbenches.
- ;Debug regressions and verification failures.
- ;Drive functional coverage closure and verification deliverables.
;REQUIRED / PREFERRED
; SystemVerilog UVM AMBA Protocols Regression Debug Coverage Closure
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Sourced from naukri
Skills
EngineeringAutoCADi2cspiverificationcprotocolsPerlASIC VerificationVerilogUVMSystem VerilogSOC VerificationVHDLRTL CodingRTL DesignProduction EngineeringAxiC plus plusahbPythonproductionmaintenanceLinux