Digital Verification Lead Engineer

Role & responsibilities

• Develop design verification methodologies and implement standard debug flows
• Work with designers in verification and validation of circuit designs
• Participate in design reviews
• Prepare design verification plan based on design specifications
• Plan and schedule assigned projects for timely completion
• Utilize the latest techniques, tools, and technologies for design verification activities
• Maintain design verification environment and track & close design bugs

Preferred candidate profile

• 10+ years experience in the semiconductor industry
• Proven track record in verifying complex designs (preferably in high volume applications) - FPGA or ASIC
• Skilled in trade-offs between quality and schedule
• Experience in constrained random test bench development
• Familiarity with SerDes and high-level protocols (e.g., PCle, USB, DP) would be advantageous
• Extensive digital verification background with some UVM experience