Digital Design Engineer RTL Design & SoC Integration

Job Location: Bengaluru, India
Experience: 4-7 Years
Employment Type: Full-time
Industry: Semiconductors / VLSI Design
Department: Engineering / ASIC Design

Job Summary

We are looking for an experienced Digital Design Engineer with strong expertise in RTL design, SoC integration, and digital IP development. The ideal candidate will have hands-on experience in Verilog/SystemVerilog or VHDL, clock and reset architecture, IP integration, RTL quality checks, and verification workflows.

The candidate will collaborate with architecture, verification, physical design, and system teams to develop robust, reusable, and high-quality digital designs for complex SoCs.

Key Responsibilities

• Design, develop, debug, and maintain RTL modules using Verilog, SystemVerilog, or VHDL.
• Develop and integrate digital IPs, including clocking and reset logic, GPIO, I2C, SPI, PWM, and other peripheral interfaces.
• Perform SoC-level integration, connectivity checks, and configuration of IPs and control registers.
• Execute RTL quality checks, including lint analysis, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC), where applicable.
• Perform formal verification and property checking using tools such as Cadence JasperGold or equivalent platforms.
• Support Engineering Change Order (ECO) implementation and Logic Equivalence Checking (LEC) for RTL and gate-level modifications.
• Develop automation scripts using Perl, Python, Tcl, or Shell to streamline RTL development and SoC integration workflows.
• Debug integration issues and collaborate with cross-functional teams to resolve design and system-level problems.
• Support functional safety requirements, design documentation, and traceability for automotive or other safety-critical SoCs, where applicable.
• Contribute to design reviews, coding standards, quality improvement, and reusable IP development.

Required Skills

• Strong fundamentals in digital electronics, RTL design, and synchronous digital design.
• Hands-on experience with Verilog/SystemVerilog or VHDL.
• Experience in SoC integration, IP integration, or subsystem-level design.
• Understanding of clocking, reset architecture, timing concepts, and control/status register configurations.
• Experience with RTL linting, CDC analysis, and RTL debugging.
• Familiarity with simulation and debugging tools such as Cadence Xcelium, SimVision, or equivalent tools.
• Scripting experience in Perl, Python, Tcl, or Shell.
• Experience with formal verification, equivalence checking, or JasperGold is desirable.

Preferred Qualifications

• Experience with clock and reset IP development.
• Exposure to automotive SoCs and ISO 26262 functional safety processes.
• Knowledge of IP-XACT and automated SoC integration methodologies.
• Experience with LEC, ECO implementation, and RTL quality sign-off.
• Experience with peripheral IPs such as I2C, SPI, GPIO, PWM, PMBus, ADC interfaces, or bus/interconnect IPs.
• A bachelor's or master's degree in Electronics, Electrical Engineering, VLSI, or a related discipline.

Candidate Profile

• Strong problem-solving and debugging skills.
• Ability to work effectively with architecture, verification, and integration teams.
• Good technical documentation and communication skills.
• Ownership of design quality, project milestones, and end-to-end execution.

Keywords

Digital Design Engineer, RTL Design, SoC Integration, ASIC Design, Verilog, SystemVerilog, VHDL, Clock Reset IP, CDC, RTL Lint, Formal Verification, JasperGold, LEC, ECO, Perl, Python, Tcl, IP-XACT, VLSI, Semiconductor Design.