DFT Trainer - Freelancer Opportunity

About Maven Silicon:

Maven Silicon is a premier institution dedicated to advancing semiconductor education and training. We are committed to nurturing future engineers and providing them with the practical skills and in-depth knowledge required to excel in the rapidly evolving VLSI industry. Our innovative training programs are designed to bridge the gap between academia and industry, ensuring our students are job-ready.

Position Overview:

Maven Silicon is seeking a highly experienced and knowledgeable DFT Trainer for a freelance engagement. This role is ideal for a seasoned professional with a robust understanding of Design For Testability (DFT) principles and methodologies. The successful candidate will be responsible for delivering engaging and comprehensive training sessions to our students, fostering their understanding and practical application of DFT concepts. This is a part-time, remote opportunity, requiring a commitment of 3-4 hours per day. We are open to candidates located across India.

Job Responsibilities:

 Develop and deliver high-quality training modules on various aspects of Design For Testability (DFT), including scan insertion, boundary scan (JTAG), built-in self-test (BIST), test compression techniques, ATPG, fault models, and test pattern generation.

 Create and maintain comprehensive training materials, including presentations, lab exercises, case studies, and assessments.

Guide and mentor students, providing clear explanations, practical examples, and constructive feedback to enhance their learning experience.

Facilitate hands-on lab sessions, ensuring students gain practical experience with industry-standard DFT tools and flows.

Assess student progress through regular evaluations, quizzes, and project work, providing timely and actionable feedback.

Stay abreast of the latest advancements and emerging trends in DFT and semiconductor testing, integrating new concepts into the training curriculum.

 Foster a positive and interactive learning environment that encourages critical thinking and problem-solving.

Collaborate with the academic team to refine the curriculum and address specific student needs.

Ensure the training program aligns with industry best practices and prepares students for real-world engineering challenges.

Requirements:

 A Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.

A minimum of 5 years of professional experience in the VLSI industry, with a significant focus on Design For Testability (DFT).

Proven experience in implementing DFT techniques in complex ASIC designs.

In-depth knowledge of DFT concepts such as scan chain design, ATPG, BIST, test compression, boundary scan (JTAG), and fault simulation.

Proficiency with industry-standard EDA tools for DFT implementation and verification (e.g., Synopsys Tetramax, Mentor Graphics Fastscan, Cadence Genus/Innovus).

 Strong understanding of Verilog/VHDL and ASIC design flow.

 Excellent communication, presentation, and interpersonal skills, with the ability to explain complex technical concepts clearly and concisely.

Demonstrated ability to train or mentor junior engineers or students.

Self-motivated, disciplined, and able to manage time effectively to deliver training sessions remotely.

Prior experience in an academic or training setting is a strong advantage.

Ability to commit to 3-4 hours of training engagement per day.

Work Arrangement:

 Type: Freelance

 Schedule: 3-4 hours per day

 Location: Remote (Open to candidates across India)

If you are a passionate DFT expert with a desire to share your knowledge and shape the next generation of VLSI engineers, we encourage you to apply.