DFT Lead

JOB DESCRIPTION :

• Minimum of 7+ years of experience in DFT implementation
• Proven experience in implementing DFT techniques such as scan insertion, MBIST, BIST, JTAG, OCC, EDT etc
• Develop DFT strategy and architecture, including hierarchical DFT.
• Experience in JTAG and iJTAG protocols and architectures.
• ATPG pattern generation, ATPG patterns verification with gate-level simulation 
• MBIST pattern generation, Pattern simulations with gate-level simulations
• BIST implementation for both AC & DC pins
• Experience working in Partition/Block/SoC level designs
• Experience in working with SSN implementation and verification.
• Experience in DFT Flows brings up from scratch (Script implementation)
• Experience with EDA tools for DFT (e.g., Siemens Mentor)
• Effective communication and leadership skills
• Collaborate with cross-functional teams to ensure DFT requirements are met