HYDERABAD · FULLTIME
DFT Lead Engineer
Bitsilica
Hyderabad · onsite · Posted 47d ago
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Undisclosed8–13 yrsfulltimeHyderabad
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Section · 01
About this role
Role & responsibilities
- 8 to 10+ Years of experience in DFT architecture, scan Insertion, and compression at the core level and SoC level.
- Experience in ATPG pattern generation and coverage analysis
- Experience with timing and no-timing simulations
- Experience in Memory-BIST
- Have an understanding of SSN architecture, clock architecture, and OCC
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Section · 02
Skills
clock architectureCompressionAtpgMbistJTAGDFTScanningcoverage analysisscan insertionBISTmemory BISTDFT ArchitectureTetraMaxoccDesign