BENGALURU · FULLTIME
DFT Integration Lead
Advanced Micro Devices
Bengaluru · onsite · Posted 4d ago
Sourced from
Undisclosed11–16 yrsfulltimeBengaluru
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Section · 01
About this role
SMTS DFT Design Engineer
Job Summary
Key Responsibilities
Preferred Experience
Academic Credentials
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
Job Summary
As a member of the S3 SoC DFx Team, the successful candidate will own/lead the DFT Design and Integration of cutting edge DFT structures including SCAN, ATPG, MBIST, BSCAN. Position includes DFT design development, data analysis and silicon debug of DFT in leading process technologies. Strong self-driving ability, should have excellent communication skills (both written and oral). Strong problem-solving skills.
Key Responsibilities
- Working closely with the DFT Architecture and the various IP Design teams to align on the DFT requirements and successfully implementing the DFT design
- Design and develop correct by construction DFT design and support DFT verification
- Working closely with the RTL designers, Verification Engineers, and PD team to find creative ways to accelerate the identification of functional defects.
Preferred Experience
- Experience and an understanding of ASIC DFT, synthesis, simulation and verification flow
- Experience is End-to-End DFT flow development/creation.
- Expert in Perl, Python, TCL, and ability to create complex flows/scripts.
- Strong EDA tools experience (Tessent, Design Compiler, Spyglass)
- Experience in DFT architecture for complex chips
- Experience in RTL development using Verilog/System Verilog having worked on RTL for IP and SoC integration
- Proficient in doing basic unit-level verification using simulations.
- Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required.
- Must have experience with integration of various IPs into complex SOCs.
- Exposure to Static timing analysis Timing closure is required.
- Scan/ATPG patterns test flows development, debug, test, and characterization
- Excellent hands-on debug skills and scripting skills are critical.
- Must have good communication skills and the ability to work in a worldwide team environment.
- Knowledge experience of low power concepts, clock gating, power gating is a plus
- Experience with post-silicon bring up is a plus
Academic Credentials
- B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering
- 11+ years experience in DFT Design
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
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Section · 02
Skills
CdcAtpgeda toolscompileripsASICdesign engineerLINTDFTcharacterizationElectronics EngineeringconstructionEvent DrivenDebugDFT ArchitectureHealthcareCommunication SkillsArchitecturedata analysisArtificial Intelligence
Section · Company
About Advanced Micro Devices
Advanced Micro Devices
Semiconductors
6k+
employees
1969
57 years old
Santa Clara,California
United States
₹26.2L PA avg
Avg at Advanced Micro Devices
About
A key player in the semiconductor industry, the company delivers advanced computing solutions addressing critical challenges across data centers, gaming, and PC markets.
Industries
SemiconductorsInternetHardware & NetworkingSoftware Product
Employee ratings
10 reviews
3.6/ 5
Culture
2.7
Career growth
2.2
Work-life
2.9
Employees rate it well for
Overall Company36Compensation & Benefits35
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