Agent
Jobs
Applied
Tracker
Profile
    1. Jobs for you
    2. Job

    Job · 18858160

    BENGALURU · FULLTIME

    DFT Engineer

    Astera Labs logo

    Astera Labs

    Bengaluru · onsite · Posted 29d ago

    Sourced fromNaukri
    Undisclosed5–10 yrsfulltimeBengaluru

    About a minute. You'll make an account on the way through.

    agent · working

    • Read this posting0.2s
    • Found the form on Naukri · 10 questions to answer1.4s
    • Decided the answers for all of them2.4s
    • Tailor your résumé to this role
    • Waiting for you

    Section · 01

    About this role

    Job Summary
    Tech Lead Design Engineer to help architect and deliver the connectivity silicon powering the worlds largest AI clusters. You'll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies. This is a high-impact technical role at a hyper-growth company. You'll partner closely with architecture, verification, DFT, and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap. If you want to ship silicon that defines AI infrastructure, this is the team.


    Responsibilities
    • RTL Design Implementation
      • Own RTL design for assigned blocks from microarchitecture through synthesis sign-off
      • Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA
      • Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality
    • Cross-Functional Execution
      • Partner with architecture to translate specifications into implementation-ready microarchitecture
      • Collaborate with verification on testplans, coverage closure, and bug triage
      • Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure
    • Technical Leadership Quality
      • Mentor junior engineers and contribute to design methodology, scripts, and best practices
      • Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments
      • Drive structured, data-driven design decisions in support of aggressive tapeout schedules


    Basic Qualifications
    • Bachelors degree in Electrical Engineering, Computer Engineering, or related field
    • 5+ years of digital design experience, including at least one full chip from spec to tapeout
    • Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows
    • Hands-on experience with timing closure, CDC, lint, and low-power design techniques
    • Solid understanding of high-speed serial interfaces PCIe, Ethernet, or similar and SoC integration


    Preferred Qualifications
    • MS or PhD in Electrical Engineering or Computer Engineering
    • Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs
    • Familiarity with formal verification, emulation, or assertion-based methodologies
    • Background in advanced process nodes 7nm, 5nm, or below
    • Strong debug skills across pre-silicon and post-silicon environments


    Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

    Sourced from naukri

    Section · 02

    Skills

    CdcAI infrastructureformal verificationphysical designpcscomputer engineeringdigital designCOSMOSPCIEdesign engineerLINTRTL CodingRTL DesignDFTLow-Power DesignBISTDebugelectrical engineeringArchitecturehyperArtificial Intelligence

    Section · Company

    About Astera Labs

    Astera Labs logo

    Astera Labs

    San Jose

    CR

    About

    Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable.

    Industries

    AI InfrastructureAutomotiveElectronicsIntelligent SystemsSemiconductor

    Find them on

    WebsiteLinkedIn

    DFT Engineer · waiting for your command