HYDERABAD · FULLTIME
DFT Engineer CH, UK
Kandou Ai
Hyderabad · onsite · Posted 12d ago
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Not disclosed5–7 yrsfulltimeHyderabad
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Section · 01
About this role
Challenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We're an innovative leader in high-speed and energy efficient chip-chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today, but of tomorrow too. If you love to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you.
We are actively seeking a resourceful DFT Engineer based in Lausanne, Switzerland or UK
Key Responsibilities:
We are actively seeking a resourceful DFT Engineer based in Lausanne, Switzerland or UK
Key Responsibilities:
- Hierarchical MBIST and scan insertion, BSD implementation
- ATPG pattern generation, coverage analysis, converging to high coverage metrics
- Pattern simulations with timing
- Defining test mode timing constraints, analyzing the timing reports and converge timing
- Developing cycle accurate functional patterns using IJTAG methodology
- Closely working with the test and production engineering teams to debug and bring up devices at probe and final test
- Debugging silicon issues
- Excellent communication skills, and strong team player with can do type of attitude
- Excellent debugging skills
- Good scripting skills to develop automation
- 5+ years of DFT experience including implementation, test pattern development, and simulation
- Proven experience in contributing to DFT solution to complex designs
- Experience working with IJTAG methodologies
- Experience with hierarchical MBIST insertion, hierarchical scan insertion and scan compression methodologies
- Experience in ATPG pattern generation for different kinds of fault models, fault coverage analysis and converging to high coverage metrics
- Good debug capabilities in simulating patterns with timing
- Experience with industry standard EDA tools for DFT, timing, and simulation
- Knowledge of System Verilog
- Bachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering (equivalent or higher)
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Section · 02
Skills
Industry-standard EDA toolsFault Coverage AnalysisHierarchical MBIST insertionHierarchical scan insertionIJTAG methodologyScan compression methodologiesSystem VerilogDFTATPG Pattern generation
Section · Company
About Kandou AI
Kandou Ai
Lausanne
CH
About
Kandou AI specializes in the design of high-speed, and pin- and energy-efficient chip-to-chip links, SerDes, and associated technologies. KANDOU specializes in the design of high-speed, and pin- and energy-efficient chip-to-chip links, SerDes, and associated technologies. Demand for bandwidth in serial links has increased as industries require both high-quantity and high-quality information. KANDOU BUS has developed a unique approach to serial link design that increases the bit-rate and the reach for a given physical communications link and reduces the power consumption. As a result, more bits can be sent per unit of energy, or less energy can be used to achieve a given bit rate. Less energy means available power can be used for more speed, greater battery life, smaller dies or novel designs that shatter many of today’s constraints. Their team of scientists and engineers, based in Switzerland, the UK, and the US, is pushing the boundaries of serial links.
Industries
Artificial Intelligence (AI)ElectronicsInformation TechnologySemiconductor
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