DFT (Design for Testability) Engineer

About the Role:

GTC Informatics Private Limited is hiring experienced DFT Engineers for ASIC and SoC projects across India. These positions are open on both a full-time and contract basis, depending on client and project requirements. Experienced candidates who can join quickly are encouraged to apply.

Location : PAN INDIA

Roles & Responsibilities:

• Define and implement DFT architecture for ASIC/SoC designs
• Carry out scan insertion, compression and ATPG pattern generation
• Implement MBIST, LBIST and JTAG/boundary scan
• Run pattern simulations (zero-delay and timing) and debug failures
• Improve test coverage and work with design and physical design teams on DFT timing closure
• Support silicon test, bring-up and ATE debug with test teams

Required Skills & Experience:

• 4–10 years of experience in DFT for ASIC/SoC
• Hands-on experience with scan insertion, ATPG, MBIST and JTAG
• Experience with tools such as Siemens Tessent, Synopsys TetraMAX/DFT Compiler or Cadence Modus
• Good understanding of fault models (stuck-at, transition) and test coverage
• Knowledge of Verilog and of the synthesis and STA flow
• Good debugging and communication skills

Good to Have:

• Experience with scan compression (EDT/DFTMAX)
• Silicon bring-up and ATE debug experience
• Scripting skills in Tcl, Perl or Python

How to Apply:

Apply through Foundit, or send your updated resume to [HIDDEN TEXT]

Email subject: DFT Engineer | Total Experience | Current Location

(Example: DFT Engineer | 6 Years | Bengaluru)

Include your technical expertise, relevant project experience, current location, notice period and contact details. Please mention whether you are looking for a full-time or contract role.