DFT (Design For Testability) Engineer

We are seeking a DFT Engineer to design and implement testability structures for complex ASIC/SoC designs, ensuring high test coverage, manufacturing yield, and silicon quality across advanced technology nodes.

Required Candidate profile

Required Skills: ASIC/SoC design flow, Scan/ATPG, MBIST/LBIST, JTAG, Synopsys/Cadence/Mentor DFT tools, Verilog/SystemVerilog, fault simulation.