Dft Design Engineer

DFT Staff Engineer

A DFT Sta Engineer is responsible for designing, implementing, and signing o Designfor-

Test (DFT) architecture for complex SoCs/IPs. The role ensures that semiconductor

designs are testable, high-quality, and manufacturable, while balancing coverage,

performance, power, and cost.

Key Responsibilities

1. DFT Architecture & Strategy

• Define and implement DFT architecture at block/IP or SoC level

• Specify test methodologies (scan, MBIST, boundary scan, compression)

• Ensure testability built early into RTL design flow

• Balance trade-os between coverage, area, power, and test time

2. DFT Implementation

Perform:

• Scan insertion and stitching

• ATPG pattern generation and simulation

• MBIST / LBIST / boundary scan integration

• Develop and validate DFT timing constraints (STA)

• Execute DFT flows at RTL and gate level

3. Test Coverage & Quality

• Analyze and improve fault coverage

• Debug scan/ATPG issues and resolve coverage holes

• Optimize:

• Pattern count
• Test cost
• Test time

4. Verification & Signo

• Run DFT verification and DRC checks

• Ensure clean DFT signo (coverage, timing, power impact)

• Validate patterns using simulation and test tools

• Support DFT integration guidelines at SoC level

5. Cross-Functional Collaboration

Work with:

• RTL design

• Physical design (PD)

• Verification

• Test engineering / ATE

• Drive issue resolution across teams

• Ensure end-to-end execution of DFT flows

6. Silicon Bring-up & Debug

• Support post-silicon debug and yield improvement

• Debug tester failures and improve manufacturing coverage

• Assist customer or product teams during bring-up

Required Skills & Expertise

Core Technical Skills

Strong expertise in:

• Scan (insertion, compression)

• ATPG & fault models

• MBIST / LBIST

• JTAG / Boundary Scan (IEEE 1149.1)

• Good understanding of:

• RTL design & verification

• STA and timing closure

• SoC design flow

Tools

• Synopsys / Cadence / Siemens tools (e.g., TestMAX, Tessent, Modus)

• Simulation tools (VCS, etc.)

• Scripting: TCL, Python, Perl

Qualifications

• BSEE/MSEE (or equivalent)

• Typically 7+ years of DFT / ASIC experience (Sta-level expectation)

• Proven experience in end-to-end DFT implementation and debugging