DFT ASIC Engineering Technical Leader - ATPG - 10 to 17 years - Bangalore

Meet the Team

Join the Cisco Silicon One team and drive innovation at the heart of next-generation network devices—Cisco Silicon One™. Our unique team operates in a startup-like environment within a world-class corporation, pushing the boundaries of advanced silicon technologies. Our design center brings together all silicon hardware and software development disciplines, promoting an atmosphere of collaboration, technical leadership, and excellence.

We are redefining the networking industry and building the future of the internet for the 5G era. With Cisco Silicon One™, we deliver a unified, programmable silicon architecture—the foundation of all Cisco's future routing products. Our platform offers high-speed networking, programmability, power efficiency, and scalability for service provider and web-scale markets.

Your Impact

• Lead, mentor, and develop a team of DFT engineers responsible for designing and implementing innovative DFT features ensuring high-quality, testable, and manufacturable silicon designs.
• Drive the team through the full product lifecycle, from pre-silicon design, post-silicon debug, to production qualification.
• Collaborate with chip architects, design engineers, and verification teams to define, optimize, and standardize DFT strategies across multiple projects.
• Supervise implementation of ATPG, scan compression, memory BIST, and other advanced DFT techniques to improve test coverage and efficiency.
• Guide the debugging and root-cause analysis of silicon failures, leveraging team expertise to improve yield and reliability.
• Establish and continuously improve DFT methodologies and best practices, ensuring adoption across current and future designs.
• Foster a culture of innovation, technical excellence, and partnership within the DFT group.
• Provide regular feedback, career development support, and performance evaluations for team members.
• Represent the DFT team in cross-functional meetings and communicate key updates to management and stakeholders.

Minimum Qualifications

• BTech/Mtech. in Electrical/Computer Engineering or a related field with 10+ years of demonstrated experience.
• Proven hands-on experience with DFT features such as scan insertion, BIST, or boundary scan.
• Demonstrated experience leading and developing engineering teams, including mentoring, performance management, and project planning.
• Proficiency in the full product lifecycle, from pre-silicon design to silicon bring-up and production qualification.

Preferred Qualifications

• Experience with Automatic Test Pattern Generation (ATPG) methodologies and advanced DFT techniques.
• Strong ability to define, standardize, and implement DFT methodologies from design phase to high-volume production.
• Prior experience in leading complex technical projects and collaborating with cross-functional teams.
• Excellent interpersonal, communication, and presentation skills.
• Ability to motivate team members, promote technical growth, and manage priorities in a dynamic environment.
• Strong attention to detail and system-level understanding of networking and silicon solutions.