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    Job · 20670609

    HYDERABAD · FULLTIME

    Design Verification Engineer

    HCL Technologies

    HCL Technologies

    Hyderabad · onsite · Posted 11d ago

    Sourced fromNaukri
    Undisclosed7–12 yrsfulltimeHyderabad

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    Section · 01

    About this role

    Company: HCL Tech


    Job Summary:We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits.

    Responsibilities:

    • Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification)
    • Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage
    • Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality
    • Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues
    • Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence
    • Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment
    • Participate in code reviews and champion best practices for verification code quality
    • Stay current with the latest advancements in verification tools and methodologies

    Qualifications:

    • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus)
    • 7+ years of solid experience in Design Verification for ASICs or SoCs
    • In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines)
    • Proven ability to develop, debug, and optimize complex verification environments
    • Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal)
    • Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl)
    • Experience with formal verification tools and techniques is a plus
    • Excellent analytical and problem-solving skills with a meticulous attention to detail
    • Strong communication, collaboration, and leadership skills to effectively contribute and guide the team

    Benefits:

    • Competitive salary and benefits package commensurate with experience
    • Opportunity to work on leading-edge technologies and projects with a high impact
    • Collaborative and dynamic work environment that fosters continuous learning
    • Potential for professional development and career advancement


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    Section · 02

    Skills

    UVMSystem VerilogDesign VerificationAXI protocols

    Section · Company

    About HCLTech

    HCL Technologies

    HCL Technologies

    IT Services & Consulting

    119.0k+

    employees

    1991

    35 years old

    Noida, Uttar Pradesh

    India

    ₹11.6L PA avg

    Avg at HCLTech

    About

    We bring together the best of technology and our people to supercharge progress.

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