Design Verification Engineer

Design Verification Engineer (3-5 Years)

Position details

• Company: Raiton Semiconductor Pvt. Ltd.
• Location: Bangalore, India (client-site / hybrid, as per project)
• Experience: 3-5 years in ASIC/SoC functional verification
• Employment type: Full-time
• Apply to:[email removed]
  

Role summary

• Own block- and subsystem-level verification for IPs and SoC subsystems built on industry-standard protocols.
• Develop and maintain UVM environments; write and debug tests; drive coverage closure.
• Work directly with design, architecture and client teams to sign off features on schedule.
• Write C-based tests for processor-driven verification where the program requires it.
• Contribute to functional-safety verification activities on automotive programs.

Key responsibilities

• Develop verification plans from design specifications and protocol standards; map features to tests, assertions and coverage.
• Build, extend and maintain SystemVerilog/UVM testbenches: agents, scoreboards, reference models and sequences, using in-house and commercial VIPs.
• Verify one or more of: PCIe (Gen4/Gen5/Gen6), NVMe, DDR4/DDR5/LPDDR5, HBM2e/HBM3, RISC-V cores and subsystems, Ethernet (10G400G MAC/PCS), USB 3.x/USB4.
• Write C/C++ bare-metal tests for CPU-driven and firmware-driven verification of processor subsystems and system-level scenarios.
• Debug RTL and testbench failures to root cause; work with designers to close issues and re-verify fixes.
• Achieve and report functional and code coverage closure; analyse coverage holes and add targeted tests.
• Write SystemVerilog Assertions for protocol and interface checking.
• Run regressions, triage failures and maintain regression health across nightly and release builds.
• Participate in functional-safety verification (ISO 26262): fault injection/fault simulation, safety-mechanism verification and diagnostic-coverage evidence.
• Support gate-level simulation and low-power (UPF) verification where required by the program.
• Document verification plans, test descriptions and signoff reports to client standards.

Required skills and experience

• 3-5 years of hands-on ASIC/SoC functional verification experience.
• Strong SystemVerilog and UVM: constrained-random stimulus, transaction-level modelling, scoreboarding, factory/config-DB usage, sequence layering, phasing.
• Good working knowledge of C for embedded/bare-metal tests and DUT firmware interaction; familiarity with DPI-C.
• Hands-on verification of at least two of: PCIe, NVMe, DDR/LPDDR, HBM, RISC-V, Ethernet, USB, functional safety (ISO 26262).
• Solid understanding of digital design fundamentals, bus protocols (AXI/AHB/APB), clock-domain crossing and reset concepts.
• Experience with SystemVerilog Assertions and functional coverage (covergroups, cross coverage).
• Proficiency with at least one major simulator (Synopsys VCS, Cadence Xcelium or Siemens Questa) and a debug tool (Verdi or equivalent).
• Scripting in Python, Perl or Tcl for regression automation and results analysis.
• Experience with version control (Git/Perforce) and regression management tools.
• Ability to read and interpret protocol specifications and design documents independently.
• Clear written and verbal communication; comfortable working directly with client design and architecture teams.

Good to have

• Exposure to RISC-V ISA and privileged architecture; processor verification using ISS/co-simulation (Spike, ImperasDV or similar).
• Formal verification experience (JasperGold, VC Formal) for connectivity or property checking.
• Low-power verification with UPF: power-aware simulation, retention/isolation checks.
• Gate-level simulation and X-propagation debugging.
• Emulation or hardware-accelerated verification (Zebu, Palladium, Veloce).
• Familiarity with CXL, AMBA CHI or other coherent-interconnect protocols.
• Automotive functional-safety background: FMEDA, fault-campaign tooling (Z01X, Xcelium Safety, Questa Safe).
• Portable Stimulus (PSS) exposure.

Education

• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI or Computer Engineering, or equivalent.