HYDERABAD · FULLTIME
Design Verification Engineer - UVM/System Verilog
The Growth Hive
Hyderabad · onsite · Posted 6d ago
Sourced from
Not disclosed3–6 yrsfulltimeHyderabad
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Section · 01
About this role
Design Verification Engineer - UVM/System Verilog
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Section · 02
Skills
verificationVerilogUVMSystem VerilogDesign Verification