BENGALURU · FULLTIME
Design Verification Engineer - System Verilog
App-Ex Semiconductor
Bengaluru · onsite · Posted 85d ago
Sourced from
Not disclosed2–8 yrsfulltimeBengaluru
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Section · 01
About this role
Design Verification Engineer - System Verilog
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Section · 02
Skills
UVMSystem VerilogSOC VerificationDesign VerificationverificationReact Testing Library
Section · Company
About App-Ex Semiconductor
App-Ex Semiconductor
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