Design Verification Engineer (High-Speed Networking ASIC)

Job Title: Design Verification Engineer – High-Speed Networking ASIC

Location: Bangalore
Experience: 8–10 Years
Employment Type: Contract to Hire
Work Mode: Hybrid – Work from office Tuesday to Thursday

Job Description:

We are looking for an experienced ASIC Design Verification Engineer with strong expertise in SystemVerilog, UVM, and functional verification to work on high-speed networking ASIC IPs and subsystems.

Key Responsibilities:

• Develop UVM-based testbenches from scratch for IP and subsystem verification.

• Create verification plans, test plans, and constrained-random test cases.

• Implement SVA assertions and drive functional and code coverage closure.

• Manage simulation regressions and debug failures.

• Perform waveform analysis and root-cause verification issues.

• Collaborate with RTL design and firmware teams to resolve design issues.

Mandatory Skills:

• 8–10 years of ASIC Design Verification experience.

• Strong SystemVerilog and UVM expertise.

• Hands-on experience with Synopsys VCS and Verdi/DVE.

• SVA, functional coverage, and constrained-random verification.

• Regression management, debugging, and coverage closure.

Good-to-Have Skills:

• Ethernet, MACsec, IPSec, PCIe, or high-speed serial interfaces.

• Networking or switching ASIC verification.

• Python, Perl, or Shell scripting.

• UVM RAL, formal verification, or SoC-level verification