3G
. Design Verification Engineer Functional Verification
3iTech Global Private Limited · Bengaluru · onsite · Posted 7d ago
Not disclosed5–7 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
Position Title: Design Verification Engineer
Location: Hyderabad or Bengaluru
Work Mode: Onsite/Hybrid
Experience: 5+ years
Skills Required:
- Strong expertise in SystemVerilog, UVM and Verilog/VHDL
- Testbench development, OOP concepts, randomization, constraints and SVA
- UVM components, RAL, sequences, virtual sequences and reusable verification environments
- Functional coverage, cross coverage, coverage analysis and closure
- Assertion-based verification and debugging of design and simulation issues
- Hands-on experience with at least one PHY protocol: DDR/LPDDR PHY, PCIe PHY, USB PHY, MIPI D-PHY/C-PHY, Ethernet PHY, SerDes PHY or UFS PHY
If interested, Please share your profile to [HIDDEN TEXT]
Sourced from foundit
Skills
USB PHYcross coveragedebugging of design and simulation issuesEthernet PHYLPDDR PHYRAL sequencesreusable verification environmentsUFS PHYUVM componentsvirtual sequencesTestbench DevelopmentVerilogVHDLOop Conceptscoverage analysisSVAFunctional CoverageAssertion-based verificationConstraintsrandomizationSystemVerilog/UVMSerDes PHYMIPI D-PHYPCIe PHY