BENGALURU · FULLTIME
Design For Testability DFT
Tranzium Semi
Bengaluru · onsite · Posted 6d ago
Sourced from
₹18.0L - ₹24.0L PA4–9 yrsfulltimeBengaluru
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Section · 01
About this role
- DFT Architecture & Insertion: Develop and execute SoC-level DFT strategies, including scan chain insertion, boundary scan.
- Memory & Logic BIST: Design, integrate,
- ATPG & Pattern Generation
- Rule Compliance & Verification
- Timing Closure & Sign-off
Perks and benefits
Provident fund, Health insuranceSourced from naukri
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Section · 02
Skills
design for test