Design Engineering Manager

• Lead and mentor a team of RTL design engineers across multiple SoC projects.
• Own the design execution from specification to RTL handoff, ensuring functionality, quality, and schedule adherence.
• Define and implement RTL design methodologies, coding guidelines, and best practices for consistency and reuse.
• Collaborate with architecture, verification, DFT, and physical design teams to ensure clean integration and design closure.
• Drive timing, power, and area optimization in collaboration with backend and architecture teams.
• Review specifications, micro-architecture, and RTL implementation for completeness and quality.
• Manage project planning, tracking, and reporting for design deliverables and milestones.
• Champion AI- and automation-driven improvements in design quality, linting, and performance validation.
• Contribute to recruitment, mentoring, and capability building within the design organization.
• Promote a culture of technical excellence, ownership, and collaboration across teams.

Requirements/Qualifications:

• Bachelors or Masters degree in Electrical/Electronics Engineering or related discipline.
• 12-15 years of relevant industry experience, including 2-3 years in technical or people leadership roles.
• Strong hands-on experience in RTL design (Verilog/VHDL/SystemVerilog) and SoC/Subsystem development.
• Solid understanding of ARM CPU-based architectures, AMBA interconnects (AXI, AHB, APB), and PCIe protocols.
• Proficiency in Synthesis, STA, and timing closure flows.
• Experience with linting, CDC, DFT, and low-power design techniques.
• Familiarity with C/C++ modeling and design validation environments preferred.
• Working knowledge of AI/ML-based design optimization or automation scripting (Python/TCL/Perl) is a plus.
• Excellent analytical, communication, and cross-functional collaboration skills.
• Highly self-driven, detail-oriented, and committed to design quality and schedule delivery.